Integrated circuit technology has provided a basis for the design of increasingly miniaturized systems, often providing capabilities impossible or impractical on a larger scale. As technology has progressed, the need for ever smaller, ever more complex systems has grown, requiring greater and greater density of integrated circuit technology. As the geometries of integrated circuit devices shrink and the capability to provide more function on a single integrated circuit grows, the need arises to provide designers with tools to facilitate the design of more complicated integrated circuit chips. This capability is provided by computer aided design systems.
Integrated circuits are often designed by the designer in a modular fashion. The designer breaks up the design into small, manageable pieces and captures each such piece as a module. A completed design may comprise many such modules, and modules may further comprise other modules, etc. This "nested" modular approach is particularly useful when a design is highly repetitive, since a relatively simple module may be designed and debugged, then replicated many times. This allows both a high degree of confidence in the finished design and a relatively low level of effort required to complete it.
Computer-aided design systems, hereinafter referred to as CAD systems, are well known in the present art. Such systems are in wide use in a number of engineering disciplines for the purpose of facilitating the design of such things as: electronic circuits and circuit boards (electronic CAD, or ECAD systems), mechanical systems (mechanical CAD, or MCAD systems), software (computer-aided software engineering, or CASE), and integrated circuits (also known as ECAD systems). Of particular relevance to the present invention are those ECAD systems used to design, simulate and layout integrated circuit chips.
ECAD systems of this type have been in use for many years. Specific examples of such systems include ECAD systems provided by Mentor Graphics, Inc. of Beaverton, Oreg., Valid Logic Systems of Mountain View, Calif., and LSI Logic Corp. of Milpitas, Calif., among others. In all cases, these ECAD systems comprise a set of software tools running on a computer-based workstation.
Typically, such tools include a schematic editor, a circuit compiler, a linker, a simulator, and layout tools. The normal flow of operation is "serial" in that the designer runs the schematic editor to create a design, which is stored in a design dataset. Then the designer exits the editor and runs a compiler which processes the design dataset producing another design dataset. This is then "linked" which produces yet another design dataset, and so on.
An example of such software tools is given by the MDE (Modular Design Environment) system produced by LSI Logic Corp. of Milpitas Calif. This system runs on a Sun Microsystems workstation, running the UNIX operating system and the SUNVIEW windowed graphical user interface, and includes a schematic editor (LSED), compiler, linker, logic simulator (LSIM), layout editor, bonding editor, floorplanning utility, and design rule checker.
This serial mode of operation is depicted in FIGS. 1 and 2. In FIG. 1, an input dataset (Design Dataset A) is operated on by Program A to produce another dataset (Design Dataset B). This new dataset is then operated upon by Program B to produce another design dataset (Design Dataset C), and so forth. FIG. 2 shows serial operation of a number of Processes (A, B, C, D).
Because of the serial nature of the dataset production, sometimes referred to as "batch processing" or "batch-mode", any program which produces a dataset must run to completion before another program may operate on its output. As a result of this mode of operation, a great deal of time is spent loading programs and moving data in and out of memory. This process can be quite time consuming, especially as designs grow in complexity.
Designers spend most of their integrated circuit design time engaged in a process which has become known as an "edit-compile-simulate" loop. This process involves creating and/or modifying one or more schematic diagrams with a schematic editor, compiling and linking the newly entered/modified design, and then running a simulator to determine whether or not the new design will perform as expected. If not, as is often the case, or if there are some enhancements or improvements to be made, the designer will return to the start of the process; re-editing, re-compiling and re-simulating repetitively until he is satisfied that the design performs as expected.
Another reason designers spend a great deal of time in the "edit-compile-simulate" loop is that many designers will test a design incrementally as it is created by simulating any previously design work along with some new design work. In this manner, confidence in the design is established in small steps, requiring a great deal less effort and insight at any given time than trying to test (and debug) a large design all at once. A designer or group of designers may make many cycles through this process before completing a design.
Because of the repetitive nature of the design actions taken in creating an integrated circuit design, any reduction in the amount of time required to perform any of these repeated steps will reduce the total design time by an amount as many times greater than the time savings as the number of cycles through the edit-compile-simulate process experienced by the designer.
Recently, some steps have been taken to improve the speed of ECAD systems in their time-consuming and repetitive operations. Some such steps include the design of faster, more efficient batch-mode compilers and linkers.
An example of such an improvement is incremental compilation, whereby only portions of a design which have been modified are compiled, eliminating a large portion of the data transfer and computing load required to process a modified design.
While incremental compilation provides significant time advantages over batch-mode compilation for small changes involving only one or a few modules in a large design, batch-mode compilation can be faster when design changes are extensive, or for initial compilation of a large design. As a result, any system which relies exclusively on either technique pays a penalty when the extent of design changes indicate that the other technique would be more appropriate.
Another common weakness in many present ECAD systems is that the design process is divided into two relatively isolated processes: design and layout. The design part of the process involves schematic capture, compilation, and linking as described previously herein; while the layout part involves layout floorplanning, component placement, signal routing, analysis of the layout for parameters such as parasitic capacitance, and back-annotation of the original design with information derived during the layout process. After the layout, the designer will likely re-simulate for the purpose of locating any layout-induced problems. If there are any, the edit-compile-simulate process will be repeated, this time extending the process to include layout. Because of the relative isolation of the layout process from the rest of the design process, layout is also performed serially, often being performed using software tools (programs) having user interfaces which bear little or no resemblance to those of the software tools used during the design process. An example of a floorplanner is found in commonly-owned U.S. Pat. No. 4,918,614, entitled HIERARCHICAL FLOORPLANNER, issued on Apr. 17, 1990 to Modarres, Raam and Lai.
Much of the design process is repetitive or predictable. The designer makes changes to a circuit design, then compiles, links, simulates, etc. This process usually requires the designer to run the same programs and provide them with the same or similar inputs over and over. This process of manually running programs and re-entering input parameters, re-executing processes which have already been performed before and which have already provided much the same results, etc., can be quite time-consuming.